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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DSP48E1 Switching Characteristics
Table 33: DSP48E1 Switching Characteristics
Speed Grade
Symbol
Description
1.0V
0.9V
Units
-3
-2/-2L
-1
-1M
-2L
Setup and Hold Times of Data/Control Pins to the Input Register Clock
T DSPDCK_A_AREG / T DSPCKD_A_AREG
T DSPDCK_B_BREG /T DSPCKD_B_BREG
T DSPDCK_C_CREG /T DSPCKD_C_CREG
T DSPDCK_D_DREG /T DSPCKD_D_DREG
T DSPDCK_ACIN_AREG /T DSPCKD_ACIN_AREG
T DSPDCK_BCIN_BREG /T DSPCKD_BCIN_BREG
A input to A register CLK
B input to B register CLK
C input to C register CLK
D input to D register CLK
ACIN input to A register CLK
BCIN input to B register CLK
0.24/
0.12
0.28/
0.13
0.15/
0.15
0.21/
0.19
0.21/
0.12
0.22/
0.13
0.27/
0.14
0.32/
0.14
0.17/
0.17
0.27/
0.22
0.24/
0.14
0.25/
0.14
0.31/
0.16
0.39/
0.15
0.20/
0.20
0.35/
0.26
0.27/
0.16
0.30/
0.15
0.33/
0.18
0.41/
0.18
0.20/
0.22
0.35/
0.27
0.30/
0.16
0.32/
0.15
0.38/
0.12
0.51/
0.16
0.31/
0.21
0.46/
0.20
0.31/
0.12
0.34/
0.16
ns
ns
ns
ns
ns
ns
Setup and Hold Times of Data Pins to the Pipeline Register Clock
T DSPDCK_ { A, B } _MREG_MULT /
T DSPCKD_ { A, B } _MREG_MULT
T DSPDCK_ { A, D } _ADREG /
T DSPCKD_ { A, D } _ADREG
{A, B} input to M register CLK
using multiplier
{A, D} input to AD register CLK
2.04/
–0.01
1.09/
–0.02
2.34/
–0.01
1.25/
–0.02
2.79/
–0.01
1.49/
–0.02
2.79/
–0.01
1.49/
–0.02
3.66/
–0.06
1.94/
–0.23
ns
ns
Setup and Hold Times of Data/Control Pins to the Output Register Clock
T DSPDCK_{ A, B }_PREG_MULT /
T DSPCKD_{ A, B } _PREG_MULT
T DSPDCK_D_PREG_MULT /
T DSPCKD_D_PREG_MULT
T DSPDCK_{ A, B } _PREG /
T DSPCKD_{ A, B } _PREG
T DSPDCK_C_PREG / T DSPCKD_C_PREG
T DSPDCK_PCIN_PREG / T DSPCKD_PCIN_PREG
{A, B,} input to P register CLK
using multiplier
D input to P register CLK
using multiplier
A or B input to P register CLK
not using multiplier
C input to P register CLK not
using multiplier
PCIN input to P register CLK
3.41/
–0.24
3.33/
–0.62
1.47/
–0.24
1.30/
–0.22
1.12/
–0.13
3.90/
–0.24
3.81/
–0.62
1.68/
–0.24
1.49/
–0.22
1.28/
–0.13
4.64/
–0.24
4.53/
–0.62
2.00/
–0.24
1.78/
–0.22
1.52/
–0.13
4.64/
–0.24
4.53/
–0.62
2.00/
–0.24
1.78/
–0.22
1.52/
–0.13
5.89/
–0.41
5.70/
–1.42
2.37/
–0.41
2.11/
–0.36
1.81/
–0.21
ns
ns
ns
ns
ns
Setup and Hold Times of the CE Pins
T DSPDCK_{CEA;CEB}_{AREG;BREG} /
T DSPCKD_{CEA;CEB}_{AREG;BREG}
T DSPDCK_CEC_CREG / T DSPCKD_CEC_CREG
T DSPDCK_CED_DREG / T DSPCKD_CED_DREG
T DSPDCK_CEM_MREG / T DSPCKD_CEM_MREG
T DSPDCK_CEP_PREG / T DSPCKD_CEP_PREG
{CEA; CEB} input to {A; B}
register CLK
CEC input to C register CLK
CED input to D register CLK
CEM input to M register CLK
CEP input to P register CLK
0.30/
0.05
0.24/
0.08
0.31/
–0.02
0.26/
0.15
0.31/
0.01
0.36/
0.06
0.29/
0.09
0.36/
–0.02
0.29/
0.17
0.36/
0.01
0.44/
0.09
0.36/
0.11
0.44/
–0.02
0.33/
0.20
0.45/
0.01
0.44/
0.09
0.36/
0.11
0.44/
0.02
0.33/
0.20
0.45/
0.01
0.55/
0.09
0.43/
0.11
0.58/
0.12
0.39/
0.25
0.54/
0.00
ns
ns
ns
ns
ns
DS182 (v2.8) March 4, 2014
Product Specification
35
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